Team Lead Digital Design

Location:

(2628) Netherlands

Salary:

75K EUR – 90K EUR

Type:

Permanent

Main Industry:

Search Engineering Jobs

Advertiser:

microTECH Global Ltd

Job ID:

131114202

Posted On: 

18 September 2024

Job Title: Team Lead Digital Design
Position: Full time
Location: Delft, The Netherlands, fully on site or Spain, fully remote
Salary Range: 75K – 90K EUR per annum
Looking for a result-driven and conscientious Team Lead Digital Design. Someone who thrives in an environment where your proactive and can-do attitude is highly appreciated.

You must have a minimum of 2 years of Leadership experience and a minimum of 10+ years overall of industry experience.

Responsibilities:
• You will lead the Digital RF team (5 team members and consultants)
• You will work closely with the PMO and other team leads to define project milestones and ensure timely delivery of our product.
• Post-layout simulation of complex mixed-signal SOC
• Work with backend/implementation teams to address synthesis, timing, DFT issues for ASIC implementation
• Define verification and test plan, run regressions, reproduce, and debug functional and performance bugs.
• Collaborate with analog design engineers, CAD, systems engineering, test engineering and applications teams to ensure define optimal DFT, DFM features and achieve rapid silicon bring-up and time to production release
• Analyse circuit for failure root cause analysis, investigate anomalous observations in silicon across various conditions, including PVT variations, and propose solutions

Requirements:
• 2+ years of experience as a Team Lead ASIC Digital Design.
• 10+ years of experience as a Digital Design Engineer.
• Experience in ASIC Digital Front-end Design, Verification familiarity and Back-end Design (implementation).
• Experience in designing complex mixed-signal products containing analog building blocks, and microcontrollers.
• Experience with RTL and ultra-low-power designs
• Proficiency with EDA tools (Candence, Mentor) and design languages including Verilog
• You understand all design integration activities like Lint, CDC, Synthesis & ECO
• Good knowledge of digital design flow from architecture design to sign-off
• Understanding of synthesis, static timing analysis, and netlist verifications
• Understanding of digital backend flow for Floor Planning and Place & Route (PNR)
• Understanding of digital DFT/ECO flow
• Understanding of backend design flow, including RTL synthesis, clock tree synthesis, scan and DFT insertion, place and route, and netlist verification
• Strong programming and scripting skills: MATLAB, C/C++, Tcl
• Experience in setting up Power Distribution architecture, power intent specification, and validation methodology.
• Strong knowledge of clock domain crossing (CDC) techniques.
• Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, and gate level simulation.
• Understanding of ASIC test methodologies such as scan insertion, memory BIST, and test pattern generation
• Strong analytical, and problem-solving skills.
• Ability to work effectively in a fa

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