Senior CPU RTL Designer, Silicon

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 5 years of experience with computer architecture concepts, including microarchitecture, cache hierarchy, pipelining, and memory subsystems.
• 4 years of experience in professional logic design.

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 4 years of experience with object-oriented programming languages (e.g., C++ or Python).
• Experience with processor core architectures (such as ARM, x86, RISC-V, etc.) and IPs commonly used in SoC designs.
• Knowledge of general purpose operating systems such as Linux or Android.

About the Job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will contribute to CPU front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU, propose performance enhancing microarchitecture features with efficiency in mind, and work with architects and performance teams for trade-off studies. You’ll communicate pros and cons of microarchitecture enhancements, facilitate final decision making, deliver design meetings Power, Performance and Area (PPA) goals with production quality, and become familiar with state-of-the-art techniques for processor functional block. In addition, you’ll interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort. You will work closely with the functional verification team to ensure production quality designs, and with the physical design team to meet frequency, power, and area goals.

Responsibilities

• Develop and support various electronic design automation (EDA) tool infrastructure and flows.
• Collaborate with cross-functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues, etc.) in lab and simulation.
• Architect chips or chip-subsystems by analyzing data, writing specifications, coordinating, discussing with stakeholders, and creating solutions.
• Work with internal cross-functional teams including software engineering teams, external silicon partners, and Intellectual Property (IP) vendors to functionally validate and parametrically characterize the silicon and correlate that results meet predicted values.
• Lead a team of individuals, set, and communicate individual and team priorities that support organizational goals. Meet regularly with individuals to discuss performance and development, and provide feedback and coaching. 

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