The compiler team is developing an automated optimization process that adapts our unique hardware architecture to run any HPC application, with little to no code modifications required. By using iterative rounds of telemetry and optimization, our compiler is able to intelligently adapt our accelerator into a workload-specific ASIC, at runtime.
Requirements
-BSc, MSc, or PhD in computer science, computer engineering, or a related field.
-7+ years experience with software engineering, with at least 5 years in compiler engineering.
-Experience in C, C++, or another systems programming language.
-Hands-on experience with MLIR: an advantage.
-Strong algorithmic intuition with control flow graphs and code analysis.
-Responsibilities
-Design, implement, test and maintain high- and low-level optimizations and analyses to accelerate HPC applications on our dedicated hardware.
-Work with and contribute to upstream MLIR and LLVM.
-Take a leap forward with our adaptive runtime compiler and squeeze performance where it would generally not be applicable.
-Perform application benchmarking and identify new optimization opportunities, guiding the team’s roadmap.
-Collaborate closely with cross-functional teams, including software engineers, HPC application engineers, and hardware architects, to ensure alignment on project goals and requirements.
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