Principal HW Architect

Location:

(78180) France

Salary:

market rate

Type:

Permanent

Main Industry:

Search Information Technology Jobs

Advertiser:

microTECH Global Ltd

Job ID:

132863669

Posted On:

09 April 2026

A growing, innovator in the semiconductor system IP domain is searching for a key contributor to define and optimize cache coherency solutions.

You will be a leading figure in developing cutting-edge cache-coherent interconnect IP and ensuring seamless integration with other NoC interconnects and system IP, enabling efficient and coherent communication between multiple processor cores, accelerator cores, and functional units.

You will collaborate closely with hardware designers, verification engineers, software developers, product teams, and customer-facing teams to deliver high-performance, power-efficient, and reliable NoC IP solutions.

Key Responsibilities:

1. Cache Coherency Architecture
• Provide expertise and evaluate industry-standard cache coherency protocols, in addition to proprietary coherency protocol used within their highly configurable NoC IP
• Develop scalable and robust cache coherency architectures aligned with overall System-on-Chip (SoC) designs
• Analyze customer requirements for cache-coherent system architectures, including partitioning large designs into chiplets using die-to-die and chip-to-chip standards such as CHI C2C, UAlink, UCIe, and PCIe
• Define performance, power, and area (PPA) targets for configurable IP

2. NoC Integration
• Collaborate with SoC design teams to ensure seamless integration of cache coherency into system architectures
• Optimize cache coherency architecture and microarchitecture within the NoC to reduce latency and increase bandwidth

3. Performance and Power Optimization
• Analyze performance bottlenecks and power consumption challenges
• Propose and implement innovative solutions to improve overall efficiency
• Work closely with hardware and software teams to verify and optimize cache coherency mechanisms

4. Protocol Verification
• Support verification teams in defining verification strategies to ensure correctness and robustness of cache coherency protocols and their implementation within the NoC IP
• Support emulation teams in testing and debugging to validate cache coherency behavior across functional and performance scenarios

5. Cross-Functional Collaboration
• Interact with marketing and sales teams to capture customer input and understand market and product requirements
• Collaborate with hardware design, software development, and system architecture teams to address technical needs and challenges
• Provide technical expertise and support to Application Engineering teams to assist with customer integration products

6. Industry

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