Post-doc Researcher in formal modeling of microarchitectures for timing analysis of embedded systems H/F

Job title:

Post-doc Researcher in formal modeling of microarchitectures for timing analysis of embedded systems H/F

Company:

Commissariat à l’Énergie Atomique

Job description

Entité de rattachement Le CEA est un acteur majeur de la recherche, au service des citoyens, de l’économie et de l’Etat.Il apporte des solutions concrètes à leurs besoins dans quatre domaines principaux : transition énergétique, transition numérique, technologies pour la médecine du futur, défense et sécurité sur un socle de recherche fondamentale. Le CEA s’engage depuis plus de 75 ans au service de la souveraineté scientifique, technologique et industrielle de la France et de l’Europe pour un présent et un avenir mieux maîtrisés et plus sûrs.Implanté au cœur des territoires équipés de très grandes infrastructures de recherche, le CEA dispose d’un large éventail de partenaires académiques et industriels en France, en Europe et à l’international.Les 20 000 collaboratrices et collaborateurs du CEA partagent trois valeurs fondamentales :

• La conscience des responsabilités
• La coopération
• La curiosité

Référence 2025-34941Description de l’unitéThe CEA’s technology research division (DRT) develop a broad portfolio of technologies in the fields of information and communication, energy and health.
CEA technology research division leverages a unique innovation-driven culture and unrivalled expertise to develop and disseminate new technologies for industry, effectively bridging the gap between the worlds of research and industry.
CEA-List is a research institute specialized in smart digital systems, located in the heart of the Paris-Saclay science and technology cluster.Description du posteDomaineComposants et équipements électroniquesContratPost-doctoratIntitulé de l’offrePost-doc Researcher in formal modeling of microarchitectures for timing analysis of embedded systems H/FSujet de stageAs a member of a multidisciplinary technological research team comprised of experts in software/hardware analyses through the application of formal methods, you will actively contribute to a national research project dedicated to the development of a predictability toolbox. This toolbox aims to analyze the worst-case temporal behavior of microarchitectures associated with embedded RISC-V processors. These microarchitectures are generated by a flow from a partner that automatically infers synthesizable Register Transfer Level (RTL) representations of processors from their Instruction Set Architecture (ISA).Durée du contrat (en mois)24Description de l’offreYour involvement in this project will facilitate the creation of a predictability toolbox that streamlines the exploration of design trade-offs, ultimately leading to the production of highly tailored RISC-V processors designed for Internet of Things (IoT) applications and embedded platforms used in safety-critical systems. A key aspect of predictability analysis involves assessing the worst-case execution time (WCET) of a processor by examining how a given binary code progresses through successive pipeline stages. Timing Anomalies (TAs) are execution phenomena known to hinder these analyses and must be supported.Your main responsibilities will include:

• Proposing and developing an approach to generate formal models of processor

pipelines. This involves utilizing a cycle-accurate intermediate representation of
pipelines incorporating their micro-architecture optimizations. While LECA has
previously developed formal models of pipelines for TA detection within code, these models were manually created.

• Utilizing the formally generated models as part of a pipeline analysis in a static WCET analysis tool provided by a collaborative partner. Specifically, the outcomes of cache analyses will guide the identification of temporal variations to be considered in the detection of TAs within basic blocks of input code.

• Defining microarchitectural-level instructions to alleviate the presence of various types of TAs at basic-block boundaries. These instructions will play a crucial role in the exploration process of RISC-V embedded microarchitectures, particularly when targeting safety-critical systems.

You are also expected to :

• Communicate about the work to the project partners, but also work directly with the French partners of the project;

• Participate in the scientific dissemination of the team’s research results (contributions to publications in international conferences) and in the development of our innovations (writing of patents).

• To carry out your mission, you will benefit from a first class environment at CEA LIST with access to a large number of reference tools and a strong experience in the application of formal methods to the verification of properties such as temporal anomalies.

#CEA-List ; #Post-doc ; ##IoT ; #LI-CB1 ; #Post-doctorat ; #ResearcherProfil du candidatYou have a PhD in the field of electronics or embedded systems. You have significant experience in architecture and/or in the use of formal methods. You also have a first experience in the design and verification/validation of real-time applications on multicore architectures. You enjoy working in an applied research environment at the state of the art and proposing innovations and various application areas.You have acquired the following technical skills

• Computer architecture and programming: knowledge of multi/many-core architectures and their use in a context for the execution of real-time applications, worst-case execution time analysis, formalization of architecture instruction sets, knowledge of hardware architecture description languages (HDL)

• Formal methods: formal specification language, model-checking environment, SMT solvers, etc.

• Experience in terms of interaction with partners in collaborative and/or industrial projects as well as in terms of scientific publications is also expected.

Desired personal qualities :

• Ability to work in a team, while showing a good autonomy in daily life;
• Scientific curiosity, taste for technical challenges;
• Ability to understand and solve complex problems;
• Ability to take a step back and have a transverse vision;
• Rigorous work methods and a spirit of synthesis.

In accordance with the commitments made by the CEA in favor of the integration of people with disabilities, this job is open to everyone.Localisation du posteSiteSaclayLocalisation du posteFrance, Ile-de-France, Essonne (91)VilleSaclayDemandeurDisponibilité du poste03/03/2025

Expected salary

Location

Essonne

Job date

Thu, 09 Jan 2025 04:15:18 GMT

To help us track our recruitment effort, please indicate in your email/cover letter where (vacanciesineu.com) you saw this job posting.