Lead MTS Logic Design

Location:

(Vught) Netherlands

Salary:

market rate

Type:

Permanent

Main Industry:

Search Engineering Jobs

Advertiser:

microTECH Global Ltd

Job ID:

132651377

Posted On:

23 January 2026

Job Title: Lead MTS Logic Design

Location:
Netherlands

Job Type: Full time Permanent

Salary: DOE

Role Overview:

Premier chip and silicon IP provider, is seeking to hire a Lead Member of Technical Staff Logic Design Engineer to join the Security Business Unit.

Require in-depth knowledge of embedded hardware development & tools, cryptography, security protocols and security implementations.

Key Responsibilities:

-Design and implementation of complex secure silicon IP’s
-Planning: lead other digital designers, manage projects, estimate cost (effort)
-Architecture: Design block specification, documentation, have/encourage innovative ideas/patents for current and future products
-Implementation: RTL design, lint, clock domain crossing (CDC) analysis, synthesis, IP release
-Verification: work with verification team on planning and execution, simulation, debugging simulations, formal verification, preparation of technical reviews and product documentation
-Flow and methodology: work in a dynamic and interdisciplinary R&D group that influences and guides Rambus’ technical direction by understanding and contributing to flow and methodology development
-Interact with technical leaders of the company and senior staff in engineering, product management, sales and FAE’s to help ensure successful development of high value products

Experience Required:

-BS or MS degree in Hardware Engineering, Computing Science or comparable level
-5+ years of experience in the security or chip industry in relevant engineering positions at R&D centres or system laboratories
-In depth knowledge of SoC, Silicon IP and/or FPGA logic design flows
-In depth knowledge of hardware description languages (Verilog, VHDL, SystemVerilog) and scripting languages
-In depth knowledge of cryptography, security protocols and security implementations
-Good knowledge of verification flows (assertion-based design strategies, code coverage, functional coverage, test plans etc.)
-Familiarity with IP integration, IP core delivery, and handoff issues

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