12 month contract
Immediate start
Work locations: Onsite Leuven, Enschede, Duisburg
Tasks involved :
•Selection of suitable low-power DSP core IP
•Definition of digital subsystem including memory subsystem
•Investigation and definition of clock architecture to run I3C protocol based on external clock provided by I3C interface
•Digital implementation of digital algorithms (based on Matlab algorithms from customer) and proving they can run efficiently on the DSP with less than 50uW of power consumption
•The whole ASIC has a power budget of 400uW
•Assist analog team on template detection algorithm and analog/digital trade-offs
•Candidate needs to have a good understanding and experience with Hardware/Software partition, algorithm expertise and RTL design implementation.
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