Digital Verification Engineers – 12-Month Contract
Location: Remote – Europe
Contract: 12 months
Openings: 2–3 Engineers
Client: Confidential European Technology Client
We are looking for 2–3 experienced Digital Verification Engineers to join a European client on a 12-month remote contract. The project involves verification of complex digital/FPGA designs, with a strong focus on SystemVerilog/UVM and Verilog-based environments.
Key Responsibilities
-Develop and maintain digital verification environments using SystemVerilog and UVM.
-Create and execute verification plans, testbenches, test cases and regression suites.
-Develop functional and constrained-random verification for complex RTL.
-Analyse simulation results, identify failures and debug issues with design teams.
-Work closely with RTL/design engineers to ensure high-quality verification coverage.
-Contribute to verification methodologies, automation and continuous improvement.
-Support integration and verification of interfaces and systems involving Ethernet and other high-speed communications.
Required Experience
-Strong commercial experience in Digital/RTL Verification.
-Excellent SystemVerilog and UVM skills.
-Solid experience with Verilog/SystemVerilog RTL.
-Experience developing verification environments from specification through to sign-off.
-Good understanding of functional and code coverage, assertions and regression testing.
-Strong debugging skills and ability to work independently in a remote environment.
Desirable Experience
-Ethernet / networking protocols and high-speed interfaces.
-FPGA verification and/or FPGA-based systems.
-Experience in robotics, autonomous systems or embedded systems.
-Familiarity with hardware/software integration.
-Experience with simulation and verification tools such as Questa/ModelSim, VCS or similar.
-Python or scripting experience for verification automation.
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