Digital Verification Engineer

Location:

(CS 40095) France

Salary:

market rate

Type:

Permanent

Main Industry:

Search Engineering Jobs

Advertiser:

microTECH Global Ltd

Job ID:

130823275

Posted On:

18 July 2024

Position: Senior Design Verification Engineer
Location: Sophia Antipolis France
Contract: Permanent

We are working with a company that offers a dynamic and challenging work environment for experienced professionals.
Their employees receive competitive compensation and benefits, and the ability to be an important part of an increasingly larger global team. They are on the leading-edge of the System-on-Chip (SoC) movement, and working with some of the world’s largest and most technically advanced customers.

They are currently looking at building a new Team in the South of France and are looking for different profiles.

As a Senior Design Verification Engineer, you will work with an expert team to design and deliver interconnect & memory
hierarchy solutions for some of the world’s most sophisticated mobile, telecom, automotive, and consumer SoC designs. You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day amazed at all the places where your creations end up. You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you will no longer be stuck in a silo or just a cog in the machine. Your coworkers will be an experienced team of industry experts that love what they do.

Key Responsibilities:
– Advanced UVM based test bench development and debugging
– Defining, documenting, developing and executing RTL verification test/coverage at system level
– Performance verification and power-aware verification
– Triaging Regressions, Debugging RTL designs in Verilog and SystemVerilog
– Help improve and refine verification process, methodology, and metrics
– UVM expertise on complex SoC projects from test bench development to verification closure

Experience Requirements / Qualifications:
– 10 or more years of design and verification experience and a plus in interconnect verification experience
– Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript
– Strong RTL (Verilog) and UVM/C test bench debugging skills
– Experience integrating vendor provided VIPs for unit and system level verification
– Experience with Arm AMBA protocols
– This opportunity involves high performance, low power designs on a highly visible project

Education Requirements:
– MS degree in EE, CS, or equivalent preferred. BS degree minimum

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