Position: Digital Verification Engineer
Location: UK
Background:
Our client is an innovative interface technology company specializing in the invention, design, license and implementation of unmatched high-speed, energy efficient chip-to-chip link solutions. Their proprietary technology lowers power consumption and improves overall performance of semiconductors, unlocking new capabilities in electronic devices and systems.
I am actively seeking a resourceful Digital Verification Engineer for their office in Northamptonshire.
Key responsibilities:
– Work with Design Engineers in verification and validation of circuit designs
– Prepare design verification plan based on design specifications
– Plan and schedule assigned projects for timely completion
– Utilize latest techniques, tools and technologies for design verification activities
– Maintain design verification environment, track and close design bugs
– Develop design verification methodologies and implement standard debug flows
– Participate in design reviews
Your profile:
– 5+ years’ experience in the semiconductor industry.
– Expert in digital design verification, using standardized methodologies, i.e. UVM
– Experience in simulating mixed signal designs with real-number Verilog behavioural models is highly
desirable
– Familiarity with SerDes is highly desirable
– Experience with SystemVerilog Assertions (SVA) and formal verification is valuable
– Experience in constrained random testbench development
– Proven track record in verifying complex designs (preferably in high volume ASIC applications)
– Experience with 3rd party VIP usage is an added bonus
– Familiarity with high level protocols (e.g. PCIe, USB, DP) is an added bonus
– Bachelor of Engineering in Electronics and Electrical Engineer (equivalent or higher)
If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you, please get in touch – #
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