Digital Validation Engineer – Belgium

Location:

(3001) Belgium

Salary:

market rate

Type:

Contract

Start Date: 

asap

Contract Period: 

6 months

Main Industry:

Search Electronics Jobs

Advertiser:

microTECH Global Ltd

Job ID:

132663620

Posted On: 

29 January 2026

Job Specification
Job Title: Digital Validation Engineer

Location: Leuven, Belgium
Onsite Requirement: 3–5 days per week in the office
Contract Duration: 6 months
Type: Freelance / Contract

Required Experience: 8–10 years in FPGA design and validation
Role Overview
We are looking for an experienced Digital Validation Engineer to support an FPGA-focused project involving design adaptation, implementation, prototyping, and validation. The role requires strong independence and deep familiarity with the complete FPGA development flow, from RTL through electrical validation.

You will work closely with another FPGA expert, with a strong emphasis on prototyping and hands-on validation, including bench-level debugging and timing analysis.
Key Responsibilities

-Take existing FPGA designs, adapt them, and generate FPGA bit files.
-Own the full FPGA flow from RTL design to electrical and bench-level validation.
-Develop, analyze, and refine FPGA timing constraints in collaboration with the design team.
-Analyze timing reports and resolve timing-related issues.
-Perform FPGA prototyping, device debug, and board-level debug.
-Conduct electrical validation using oscilloscopes and digital analyzers.
-Identify root causes of design or hardware issues in an electrical validation environment.
-Write and execute C-based test software for FPGA validation.
-Develop Python-based scripts and tools to support testing and validation activities.
-Use FPGA debug tools effectively to isolate and resolve issues.Required Skills & Experience

-Proven experience with the complete FPGA flow (RTL 8594; synthesis 8594; place & route 8594; validation).
-Strong digital design expertise using VHDL, Verilog, and/or SystemVerilog.
-In-depth understanding of FPGA timing concepts, including:

-Timing constraints
-Clock domain crossings
-Clock generation
-Combinatorial loops
-Hands-on experience with:

-Synplify synthesis tool
-Vivado Place & Route
-Xilinx FPGAs
-Strong background in electronics fundamentals and hardware debugging.
-Experience with FPGA-related debug tools.
-Familiarity with bench-level validation using oscilloscopes and logic/digital analyzers.
-Experience with revision control tools (e.g. SVN) and running compute jobs.

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