Digital RTL / SoC Design Engineer – 12-Month Contract

Location:

(V94 RT99) Ireland

Salary:

market rate

Type:

Contract

Start Date:

asap

Contract Period:

6 months

Main Industry:

Search Information Technology Jobs

Advertiser:

microTECH Global Ltd

Job ID:

133423419

Posted On:

09 September 2026

Digital RTL / SoC Design Engineer – 12-Month Contract

Location: 100% Remote – Europe
Contract: 12 months
Client: European Technology Company
Positions: 2–3 Engineers

We are seeking experienced Digital RTL / SoC Design Engineers to join a European technology client for an initial 12-month contract.

The engineers will work on the design and development of advanced SoC and FPGA-based products, with applications across Ethernet/networking and robotics. This is a hands-on RTL design role, working closely with verification, architecture, FPGA and embedded software teams.

The position is 100% remote, with candidates required to be based within Europe.

Key Responsibilities

-Develop high-quality RTL designs for SoC and FPGA-based systems.
-Design, implement and integrate digital IP and SoC subsystems.
-Work from architectural specifications through to RTL implementation and integration.
-Develop and maintain Verilog/SystemVerilog RTL.
-Design digital logic for Ethernet and high-speed networking applications.
-Contribute to hardware architectures for robotics and intelligent/embedded systems.
-Perform RTL simulation, debugging and synthesis analysis.
-Work closely with verification engineers to define and resolve design issues.
-Collaborate with FPGA, firmware and embedded software teams.
-Support design reviews, technical documentation and integration activities.
-Analyse timing, area, power and performance requirements.
-Participate in bring-up and debugging of designs on FPGA/SoC hardware where required.

Essential Skills & Experience

-Strong commercial experience in Digital RTL Design.
-Excellent knowledge of Verilog and/or SystemVerilog.
-Proven experience designing SoC, FPGA or ASIC-based digital systems.
-Experience with RTL development, simulation and synthesis.
-Strong understanding of digital design principles, including:

-Clock-domain crossing (CDC)
-Reset strategies
-FIFOs and buffering
-State machines
-High-speed data paths
-Timing constraints
-Pipeline architecture
-Experience working across the full RTL development lifecycle.
-Ability to work effectively with verification and system-level engineering teams.
-Strong debugging and problem-solving skills.

Desirable Experience

Experience in one or more of the following would be highly advantageous:

-Ethernet, including 1G/10G/25G/100G or higher-speed Ethernet.-

To help us track our recruitment effort, please indicate in your email/cover letter where (vacanciesineu.com) you saw this job posting.