Job Title: Digital RTL Engineer
Position: Full time – Permanent
Location: Madrid, Spain
Salary Range: 35K – 40K EUR per annum
Responsibilities:
– Implement ASIC / SoCs / FPGAs for multiple products, starting at the specification & design phase, continuing through technology selection, implementation, and validation. Innovation in performance, power and cost to build the best possible product is a must.
– Participate in all phases of ASIC / FPGA design flow (Synthesis, Place & Route, and Timing Closure) as required.
– Work with backend teams to address any layout and timing issues for ASICs.
– Verification by emulation with FPGAs in the lab.
– Involvement in lead-up, validation, characterization and qualification phases of ASICs.
Knowledge and Skills
•ASIC / FPGA / SoC System integration experience.
•Strong Silicon/ASIC design experience.
•One or more of the following:
– Networking, Wireless, Modem, video CODEC, and Logic design experience.
•Experience with Verilog and System Verilog.
•Experience with latest simulation and verification methodologies (OVM, UVM).
•Experience with EDA tools such as HDL Synthesis (Synopsys DC), HDL simulators (VCS, Questa, IES), HDL Lint tools (Spyglass), FPGA tools (Xilinx Vivado, Altera Quartus II)
•Demonstrated ability to deliver a product from concept to production.
•Demonstrated ability to work in a dynamic environment that includes working with changing needs and requirements.
•Excellent English communication skills both written and verbal.
•Strong software design and skills are nice to have.
Required title: MSc in Electronics, Electrical, Computer Engineering or relevant field.
Required expertise: at least 4 years in similar tasks.
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