(CONTRACT) UVM Verification Engineer

Location:

(9500) Austria

Salary:

market rate

Type:

Contract

Start Date:

asap

Contract Period:

6 months

Main Industry:

Search Information Technology Jobs

Advertiser:

microTECH Global Ltd

Job ID:

132420270

Posted On:

05 November 2025

Job Description

Job Title: UVM Verification Engineer
Location: Austria
Duration: 6 months
Extension: Yes
Start: ASAP
Remote: Yes

About the Job
For our client in Austria, we are looking for a Senior Verification Engineer to join their team. The role will be responsible to their Austria site but work can be performed remotely.

This role will require an engineer to have strong knowledge in random functional and formal verification.

Tasks

• Develop SystemVerilog/ UVM compliant verification environments

• Creation of verification plans and execution of coverage closure

• Provide relevant reports to show progress

• Run regressions / help set up automatic regressions and debug failures / drive debugging

• Run verification environments quality checks and improve environment to reach ASIL-D level for verification environment

• Simulate and debug existing legacy simulations/ code

Skillset

• Proven working experience within the semiconductor industry in constraint random functional and formal verification

• Expertise in hardware verification using SystemVerilog/ UVM

• Knowledge of using regression and coverage analysis tools as well as knowledge of test bench qualification

• Working experience in international and cross-functional technical teams within a multi-cultural environment

Deliverables

• Testcases ready for regression

• Qualified verification environment using SystemVerilog/ UVM

• Verification sign-off report fulfilling defined KPIs (e.g. 100% coverage)

• Intermediate reports and debug of failing test cases, coverage gap analysis

• Continuous, pro-active maintenance of agreed JIRAs and updates at least two times per week

• Weekly report about status to technical lead

Tools

Questasim, Xcelium, Vmanager Enterpris

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