(CONTRACT) Digital IC / ASIC Design Engineer

microTECH Global Ltd

(Paris) France
market rate
Start Date: 
Contract Period: 
6 months
Main Industry:
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microTECH Global Ltd
Job ID:
Posted On: 
05 September 2023

Job Title- Digital IC design engineer
Contract type – Contract
Starting Date – ASAP
Location- France/Remote

Job Description
For our client in France, we are looking for verstile and technically rounded Design Engineer with knowledge of transition works to Physical and Back-End teams. The successful Engineer will work and build new product definitions and design along with the likes of Project/Programme Managers, with Architects and Designers to name but a few.

Job function
Within the client’s design team, you will work alongside country-wide on-site teams as well as world-wide off-site teams, developing top-line CMOS communications ASICs for specialist communications clients within a core, indispensable and dedicated market. The candidate will be sporadically involved in the architecture definition, design and verification of the ASIC digital sub-blocks in close collaboration with the mixed-signal and digital IC design engineers.

Core tasks
Contribute towards all area of the ASIC design flow including specification, core function definitions as well micro-architecture of the digital sub-blocks
RTL design of sub-blocks (Verilog/System-Verilog for RTL micro-architecture)
Expansion and extension of detailed and targeted verification plans that will align with the defined circuit architecture and specifications
SDC constraints
Definition or top an blok-level self-checking test benches RTL and gate-level netlist
Participate to the evaluation of the fabricated ASIC in specialised and product-market defined measurement lab
Design, Verify and and move high end market ASICs
Design reviews
Documentation for QA


Ideally MSc/above qualifications for ASIC/Semiconductor based core tech such as Engineering or equivalent as well as a minimal level or graduation of Junior Engineer (Engineer, Senior, Principle level etc.)
ASIC full-flow product definition and design for micro-architecture definition, planning, RTL design and verification
Well developed knowledge of relevant HDLs (VHDL or Verilog) and scripting languages (TCL, Perl, Python etc.)
Constant and thorough use of SystemVerilog
Experience of UVM methodology is a plus
Strong skills and confident utilisation of analytical and problem-solving skills
Previous experience working on Digita IC projects also addding and utilising elements from an with Mixed-Signal ICs such as ADCs, DAC and/or RF comms such as transceivers is a pstrong bonus
Project experience with Cadence or Synopsys RTL design flow is a plus
You are a team player with a critical attitude and sense of initiative

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