ASIC Layout Lead

Location:

(D08 T6YA) Ireland

Salary:

market rate

Type:

Permanent

Main Industry:

Search Engineering Jobs

Advertiser:

microTECH Global Ltd

Job ID:

131244814

Posted On: 

18 October 2024

Job Title: ASIC Layout Lead
Location: Dublin, Ireland
Job Type: Full-Time
Experience Level: Individual Contributor

Company Overview:
My client are a global leader in the semiconductor industry, providing innovative solutions that power a wide range of markets including consumer electronics, IoT, automotive, network infrastructure, and more. My clients team excels in delivering high-performance, reliable products that meet the demands of a rapidly evolving technology landscape.

Job Summary:
We are looking for an experienced ASIC Layout Lead to join their Dublin team. In this role, you will collaborate with cross-functional teams to develop cutting-edge Ultra-Wideband (UWB) products, taking them from concept through to volume production. You will have key responsibilities in both top-level SOC and block-level floor planning, ensuring high-quality, efficient design and verification.

Key Responsibilities:
Layout Design & Verification:
– Work closely with Analog/RF Design Engineers to optimize the design and layout of complex RF and mixed-signal blocks.
– Deliver high-quality RF/Analog systems utilizing industry-leading methods for layout and physical verification.
– Own full top-level SOC planning as well as detailed block-level layouts.
– Conduct comprehensive verification and debugging from block level to full SOC.
– Lead and document layout design reviews, ensuring robust design processes and high standards.

Interpersonal:
– Collaborate effectively with the RF/Analog design team to deliver designs that meet specifications and project deadlines.
– Operate both independently on complex tasks and as part of a cohesive team.
– Mentor junior layout engineers and manage relationships with external layout contractors.
– Drive productivity improvements through the development of better methodologies, efficient tool use, and clear documentation.

Qualifications:
– Bachelor’s degree in Electronic Engineering or a related field.
– 10+ years of relevant industrial experience in ASIC Layout Design.
– Expertise in the Cadence Virtuoso suite and Calibre verification tools.
– Extensive experience in analog/mixed-signal layout on advanced CMOS nodes (40nm and below).
– Strong understanding of layout-dependent effects (LDE), isolation, matching, parasitics, EM, and IR drop.
– Familiarity with high-frequency RF design and layout verification checks (DRC/LVS).
– Strong analytical and debugging skills.
– Experience with Skill coding is a plus.

Why Join Them?
We are dedicated to driving innovation in wireless communication and semiconductor technology. As part of our global team, you will have the opportunity to work on cutting-edge projects, with ample room for personal and professional growth. Join us in shaping the future of #

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