Analog Mixed Signal IC Design Engineer

Location:

(28001) Spain

Salary:

market rate

Type:

Permanent

Main Industry:

Search Engineering Jobs

Advertiser:

microTECH Global Ltd

Job ID:

132731004

Posted On:

27 February 2026

Job Title

Analog / Mixed-Signal Design Engineer

Location

Spain (Onsite role with hybrid flexibility)

Company Overview

A confidential semiconductor IP company developing high-speed connectivity solutions for advanced computing, AI/ML, HPC and automotive applications. The business focuses on cutting-edge analog and mixed-signal IP implemented in advanced CMOS technology nodes.

Role Overview

The company is expanding its Analog and Mixed-Signal R&D team in Spain and is seeking an Analog / Mixed-Signal Design Engineer to support the development of next-generation SerDes and wireline connectivity IP.

This is a hands-on technical role, working closely with system architects, digital designers, physical design, and test teams to deliver first-pass silicon success on advanced process nodes.

Key Responsibilities

-Design and optimise high-speed analog and mixed-signal circuit blocks for SerDes applications
-Translate SerDes standards into transceiver architectures and detailed block specifications
-Develop power and area-efficient circuit architectures
-Collaborate closely with digital, layout, system and test engineers
-Support layout implementation, addressing parasitics, matching, stress and reliability
-Develop and execute simulation and verification strategies
-Support silicon validation and electrical characterisation
-Document design methodologies and present technical results as required
Requirements

-MSc or PhD in Electrical or Computer Engineering (or related discipline)
-Minimum 4 years’ hands-on analog IC design experience
-Strong transistor-level CMOS / FinFET design expertise
-Experience with SerDes-related sub-blocks such as CTLE, DFE, FFE, PLL, DLL, VCOs, DAC/ADC-based TX/RX
-Solid understanding of high-speed signalling and Serializer/Deserializer concepts
-Proficiency with SPICE simulators and simulation methodologies
-Layout-aware design experi

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