Analog Layout Manager

Location:

Reading (RG2) – Berkshire, South East, United Kingdom

Salary:

market rate

Type:

Permanent

Main Industry:

Search Information Technology Jobs

Advertiser:

microTECH Global Ltd

Job ID:

130750277

Posted On:

02 July 2024

This client are innovators in high-speed chip-chip link solutions for multiple market sectors.

They are seeking an Analog Layout Manager to lead their teams in the UK and Switzerland.

Key Responsibilities:

* Lead an experienced multi-site analog layout team (including hiring, resourcing, scheduling, upskilling, mentoring, performance reviews, reporting and engineering execution)
* Work closely with architecture, analog design, digital design, and verification teams to identify design gaps, design flows gaps and implement improvement actions, i.e., ensure delivery of high-quality designs
* Support IP and chip level integration, coordinate with other teams on deliverables and schedule for IPs
* Custom layout and verification of analog circuits, cells, blocks and IP for multi-Gigabit high speed chip to chip communication links (SerDes up to and beyond 28Gb/s and/or memory IO) in advanced semiconductor technology nodes
* Interact closely with the analog design team to understand requirements and implement solutions
* Continuous improvement of layout methodologies to meet ever increasing demand of quality and efficiency
* Key interface and bridge between Analog Layout and other teams. Manage workload and schedules, report to internal management team and external customers
Ideal Experience:

* Experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers
* Expertise in layout of high-speed/frequency circuits such as amplifiers, oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks such as biasing, buffers, regulators, filters, data converters
* Understanding of layout approaches and techniques for high-speed circuits, matching constraints, minimization of parasitics, power grids and ESD requirements
* Ideally, experience on modern semiconductor process technologies including 16nm, 7nm & 5nm
* User of EDA tools for design and verification such as Cadence Virtuoso, Calibre DRC/LVS, QRC
* Understanding of parasitic extraction and modelling, Electro migration, IR drop, ESD and related concepts
* Knowledge of Product Development Life Cycle and representing the analog layout discipline at project gate exits and final sign-off, inc. tape-out
* Skilled in managing a technical team in delivering quality designs to deadlines
* Experience in leading and working with teams across different geographical sites
* Project management experience would be beneficial
Additional Skills:

* Excellent organisational skills to manage team workload and report to internal management team
* Strong communicator and team leader
* Self-motivated with the ability to lead and develop a team
* Empathy and listening
* Self-management

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