Senior Formal Verification Engineer

Location:

(08034) Spain

Salary:

market rate

Type:

Permanent

Main Industry:

Search Information Technology Jobs

Advertiser:

microTECH Global Ltd

Job ID:

133117058

Posted On: 

23 June 2026

We are seeking a Senior Formal Verification Engineer to play a key role in verifying advanced AI and silicon technologies that will power the next generation of intelligent systems.

Job title: Senior Formal Verification Engineer

Location: Barcelona, Spain (also open to Rome, Italy, Limerick, Ireland and Munich, Germany)
Working Model: Hybrid and Remote option available
Experience: 5+ Years

Please note: Applicants must already have the right to live and work in the EU. Unfortunately, visa sponsorship is not available for this position.

About the Role

We are seeking a Senior Formal Verification Engineer to help define and drive formal verification strategies for next-generation AI and semiconductor platforms.

Working closely with architects, designers, and verification teams, you will contribute to IP, subsystem, and SoC-level verification using advanced formal methodologies.

Key Responsibilities

-Define and implement formal verification strategies across IP, subsystem, and SoC projects.
-Develop verification plans from architectural and design specifications.
-Write, debug, and maintain SystemVerilog Assertions (SVA).
-Analyse coverage results and collaborate with design teams to close coverage gaps.
-Support design integration, test vector delivery, debugging, and regression activities.
-Develop scripting and automation solutions to improve verification workflows.
-Contribute to methodology development and adoption of advanced verification techniques.
-Participate in technical reviews and mentor junior engineers.
-Collaborate with globally distributed engineering teams.
Requirements

Essential

-Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
-5+ years of Formal Verification experience.
-Strong expertise in:

-Formal Verification methodologies
-SystemVerilog and SVA
-Formal assumptions and constraints
-Scripting and automation
Technical Knowledge

-Deep understanding of formal verification for algorithms, protocols, and SoC-level designs.
-Experience with:

-Low Power Verification
-X-Propagation Analysis
-Connectivity Checking
-Register Map Verification
-Strong design knowledge of:

-CPUs
-NoC / Interconnect architectures
-Memory Controllers
-Cache architectures
-Excellent debugging and root-cause analysis skills.
Soft Skills

-Strong communicator and team player.
-Comfortable working in multicultural and remote environment

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